Gestapelte CMOS Halbleitervorrichtung und Verfahren zu ihrer Herstellung
摘要
A silicon layer (1) in a lower layer and an interconnection layer (8a) arranged in an upper layer are electrically connected through an opening (16) for contact. A silicon plug layer (15) having the same conductivity type as that of the silicon layer is embedded in the opening. The silicon plug layer is embedded in the opening by an etch back method after deposited using a CVD method. The interconnection layer in the upper layer has conductivity type different from that of the silicon plug layer. A refractory metal silicide layer (11) is formed between the upper interconnection layer and the silicon plug layer. The refractory metal silicide layer prevents pn junction from being formed between the upper interconnection layer and the silicon plug layer. <IMAGE>