METHOD FOR BUILDING A TESTING INFRASTRUCTURE FOR A SYSTEM ON A SEMICONDUCTOR CHIP

摘要

A technique is provided for building a testing infrastructure for use in testing the components of a system on silicon composed of user defined logic "UDL" components (14, 16, 18), virtual components (such as complex processors defined by netlists and having structures which are proprietary to the source) and interconnects thereof in a system self-contained on a semiconductor chip (10) having internal circuit interconnect nets (traces provided by the system chip designer), wherein the system chip includes at least one virtual component having supplied therewith a combination of functional and structural descriptions which are together inadequate to fully depict an embodiment of the virtual component.