Circuit synchronization with multiple clock signals

摘要

A data processing system having a first circuit and a second circuit that together control a third circuit by a respective first control signal and a second control signal. The first circuit issues a request signal to the second circuit to trigger initiation of the operation of the third circuit and the second circuit returns a grant signal to the first circuit to indicate that operation of the third circuit has completed. An advance controller within the second circuit serves to start to synchronize the grant signal back to the clock signal of the first circuit at one of a plurality of possible times that is selected to match the relative frequencies of the clock signals driving the first circuit and the second circuit.