发明名称 Memory requirement reduction in a SQTV processor by ADPCM compression
摘要 An SQTV processor is for converting a video signal received at an interlaced scanning frequency of 50 or 60 Hz to an interlaced scanning frequency of 100 or 120 Hz, respectively, and implementing algorithms for noise filtering and of edge definition. The process includes: an analog-digital converter (ADC) of analog input signals of luminance and chrominance; at least a field memory (FIELD MEMORY-1), or more preferably two similar field memories, where digital blocks of luminance (Y) value and blocks of values of each one of the two chrominance (U, V) components of the converted video signals are stored; one "First-In-First-Out" (LINE MEMORY) register for digital values read from the field memory containing the pixels of a whole line of each field; a noise filtering block (NOISE REDUCTION); a sampling frequency converter (SRC) of the fields from 50 or 60 Hz to 100 or 120 Hz; a conversion circuit for the vertical format (VFC), an edge definition (PE) enhancement circuit; and a digital-to-analog converter (DAC) of the processed luminance and chrominance (YUV) signals. The processor further includes a compressing and coding circuit for the converted video signals according to an adaptive differential pulse code modulation (ADPCM) scheme of the digital values to be stored in the field memory (FIELD MEMORY-1) and an ADPCM decoding and decompressing circuit for data read from the field memory (FIELD MEMORY-1). The significative reduction of the total memory requisite produced by the ADPCM pre-compression makes the entire system more readily integratable on a single chip.
申请公布号 US5889562(A) 申请公布日期 1999.03.30
申请号 US19970810029 申请日期 1997.03.04
申请人 SGS-THOMSON MICROELECTRONICS, S.R.L. 发明人 PAU, DANILO
分类号 H04N5/907;H03M7/38;H04N5/44;H04N7/01;H04N7/015;H04N7/26;H04N7/32;H04N7/34;H04N7/50;H04N9/64;H04N11/04;(IPC1-7):H04N7/01 主分类号 H04N5/907
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