发明名称 Integrated circuit device having a bias circuit for an enhancement transistor circuit
摘要 Disclosed is an integrated circuit device. According to the present invention, an integrated circuit device comprises: a high frequency electronic circuit having a first enhancement transistor, to the gate of which, at least, a bias voltage is applied; and a bias circuit, including a second enhancement transistor formed on a substrate on which the first enhancement transistor is formed, and first, second and third resistors connected in series between a positive power source and a power source ground, in which a connection point of the first and the second resistors is connected to a drain of the second enhancement transistor, a connection point of the second and the third resistors is connected to a gate of the second enhancement transistor, and voltages at the connection point of the second resistor and the third resistor or at a terminal which is closer to the power source ground is applied as a bias voltage to the high frequency electronic circuit.
申请公布号 US5889426(A) 申请公布日期 1999.03.30
申请号 US19970908720 申请日期 1997.08.08
申请人 FUJITSU LIMITED 发明人 KAWAKAMI, MASAYUKI;TSURUOKA, YOSHIYASU;ABE, HIDEO
分类号 G05F3/24;H03F3/193;(IPC1-7):G05F1/10 主分类号 G05F3/24
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