发明名称 |
High density EEPROM array using self-aligned control gate and floating gate for both access transistor and memory cell and method of operating same |
摘要 |
A high density EEPROM cell array structure utilizes a floating gate architecture for the access transistor and a double poly process in which the control gate and floating gate of both the access transistor and the memory cell are self-aligned, resulting in a much more compact cell than previously available. In addition, the process flow utilizes only two masks compared to the four mask flow utilized in the prior art. This leads to cost reduction in the fabrication process. The structure results in significantly reduced read time for the cell array.
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申请公布号 |
US5889700(A) |
申请公布日期 |
1999.03.30 |
申请号 |
US19970841887 |
申请日期 |
1997.05.05 |
申请人 |
NATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
BERGEMONT, ALBERT;CHI, MIN-HWA |
分类号 |
H01L27/115;(IPC1-7):G11C16/04 |
主分类号 |
H01L27/115 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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