| 摘要 |
<p>PROBLEM TO BE SOLVED: To improve high speed reading of a memory cell by providing a pre-charge device for rising a voltage level of a column of a memory array and connecting a state control circuit to monitor and control an output voltage of the pre-charge device. SOLUTION: Voltages in connecting points 44, 42 are in a grounding voltage when the input of an input terminal 40 is low, the output of a first NAND gate 48 is high, and a pre-charge transistor 54 is kept in an inactive state. An input voltage is risen, the pre-charge transistor 54 is activated, and the voltage an the connecting point 44 begins to rise toward VDD. When a transistor bias device 49 exists within a self timing pre-charge sense amplifier 30, the voltage in the connecting point 42 begins to rise toward VBIAS at the time point wherein the pre-charge transistor 54 becomes an active state. A sense amplifier 56 is connected for monitoring the output voltage, and the high speed reading is executed with the memory cell 32.</p> |
