发明名称 SEMICONDUCTOR MEMORY
摘要 <p>PROBLEM TO BE SOLVED: To suppress parasitic capacity of a bit line by arranging a sense amplifier in an adjacent position to a memory cell array. SOLUTION: This memory is provided with a memory cell array 1 having memory cells, a sense amplifier 17 provided in the adjacent position to the memory cell array and sensing data stored in a memory cell, a bit line control circuit 6' controlling writing data in a memory cell, and a data input/output buffer 7 outputting data sensed at the sense amplifier and supplying writing data externally supplied to the bit line control circuit.</p>
申请公布号 JPH1186584(A) 申请公布日期 1999.03.30
申请号 JP19970237031 申请日期 1997.09.02
申请人 TOSHIBA CORP 发明人 TANAKA TOMOHARU
分类号 G11C11/41;G11C7/06;G11C7/14;G11C16/06;G11C16/26;(IPC1-7):G11C16/06 主分类号 G11C11/41
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