发明名称 |
Phase locked loop with improved lock time and stability |
摘要 |
A phase-locked loop (PLL) circuit is used to synchronize a local clock frequency with an edge of a reference clock frequency, employing a phase detector to compare the local clock frequency and the reference clock frequency to generate a control signal indicative of the need to increase or to decrease the local clock frequency for phase locking thereof to the reference clock frequency. A voltage controlled oscillator (VCO) is responsive to a signal voltage derived from the control signal to vary the local clock frequency as necessary to achieve phase locking. A loop filter has a reference voltage threshold level which is pre-programmable to enable the loop filter to respond to the control signal by adjusting the signal voltage as a virtual step function toward the programmed reference voltage threshold level before application to the VCO, and then cycling up and down in a search for a stable control signal voltage to reduce the time necessary to achieve the desired phase locking.
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申请公布号 |
US5889829(A) |
申请公布日期 |
1999.03.30 |
申请号 |
US19970779907 |
申请日期 |
1997.01.07 |
申请人 |
MICROCHIP TECHNOLOGY INCORPORATED |
发明人 |
CHIAO, JENNIFER YUAN;YACH, RANDY L. |
分类号 |
H03L7/093;H03L7/089;H03L7/10;H03L7/12;(IPC1-7):H03D3/24;H03L7/00 |
主分类号 |
H03L7/093 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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