| 摘要 |
PROBLEM TO BE SOLVED: To provide the phase adjustment circuit for data and a clock capable of securing a withstanding amount to jitter and wander and coping with duty degradation as well. SOLUTION: A delay part 1 outputs plural unit delay phase difference data. A phase judgement part 3 receives all the data, observes a position where the data change, and in the case that the change point of the data and the rise of the clock get close or the sample timing of the clock is at a duty degraded point, outputs signals for advancing or delaying a data phase corresponding to a state. A column counter part 4 and a row counter part 5 output counter signals for deciding a selection unit on the column side and on the row side of the selection circuit of a data selection part 2. The data selection part 2 selects the data for which the phase margin of the data and the clock is appropriate specified by the column counter and the row counter and outputs the data after adjustment. By a delay judgement part 6, delay data for judging and comparing the delay of a delay element are instructed. |
