Apparatus and method for decreasing the access time to non-cacheable address space in a computer system

摘要

In a computer system, a multi-port bus controller interposed between a CPU, system memory, and an expansion bus detects when a CPU access is to non-cacheable address space and begins a bus cycle to access the data before receiving a "miss" from a cache coupled to the CPU. By detecting non-cacheable address space independently and in parallel with the cache miss determination, the multi-port bus controller saves from one to three clock cycles in each bus cycle that accesses non-cacheable address space.