| 摘要 |
In a multiplier unit having a preprocessor stage, a multiplier stage, and a summation stage, the multiplier stage includes a shift register, a gate component for controllably transmitting the multiplicand A in a manner determined by a bit signal of multiplier B applied to the gate component control terminal. Partial products are grouped by multiplicand digits and each digit is applied, through delay components determined by the order of the digit, to first terminals of an associated adder components. Output signals from each adder component is transmitted through a plurality of delay components and applied to second input terminals of the same adder component. In this manner, partial products Ap*Bq are assembled and the partial products (A0+ . . . AM)*Bq=A*Bq can be applied to the summation unit in a single period. When the multiplier is an integer multiple of the multiplicand, the implementation is particularly convenient.
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