发明名称 CMOS sum select incrementor
摘要 A method and apparatus for a CMOS inverter is provided for incrementing a first number by a one, three, or multiple of two. The incrementing unit includes an extract/restore unit for extracting a number of least significant bits from the first number, thereby producing a second number. The number of least significant bits extracted is determined by the incrementing value. The incrementing unit further includes an adjusting unit for adding an adjusting value to the least significant bits extracted from the first number, thereby producing an adjusted least significant bits. The incrementing unit further includes an incrementor block for receiving the second number and incrementing the second number, thereby producing a fourth number. The the extract/restore unit further for restoring the adjusted least significant bits to the fourth number, thereby producing a final result.
申请公布号 US5889693(A) 申请公布日期 1999.03.30
申请号 US19970851220 申请日期 1997.05.05
申请人 INTEL CORPORATION 发明人 JOSHI, VIVEK;KUMAR, SUDARSHAN
分类号 G06F7/50;G06F7/505;(IPC1-7):G06K7/50 主分类号 G06F7/50
代理机构 代理人
主权项
地址