| 摘要 |
A data reading circuit for a semiconductor memory device which is capable of obtaining a desired characteristic of a high speed latching sense amplifier and by which the circuit is stably operated even when a noise is inputted. The circuit includes a latching sense amplifier and a current mirror type sense amplifier for receiving output data DATA and DATAB from a memory cell array, a signal delay unit for delaying an output signal S0 from the latching sense amplifier, a comparing unit for comparing an output signal DEO from the signal delay unit with an output signal SOM from the current mirror type sense amplifier, a pulse generator for receiving an output signal COM from the comparing unit and outputting a pulse signal DLD, a controller for outputting sense amplifier control signals for driving the current mirror type sense amplifier, and a combination unit for outputting latching sense amplifier control signals for driving the latching sense amplifier.
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