发明名称 EVALUATION METHOD FOR SEMICONDUCTOR ELEMENT FORMING PROCESS
摘要 PROBLEM TO BE SOLVED: To provide a method for evaluating a semiconductor element forming process for quantitatively evaluating the degree of influence of each unit process on the unevenness of electrical characteristics of a semiconductor element formed on a semiconductor substrate by the use of a device simulator. SOLUTION: This method for evaluating a semiconductor element forming process comprises the steps of adjustably aligning impurity profiles of a gate electrode, a channel and an LDD for a MOSFET in a device simulator by using an inverse engineering method (S1 to S3), thereafter conducting a multiple regression analysis on unevennessΔVth of the threshold voltage of the MOSFET on a simulator (S4), and calculating the (S5) degree of influence of unevenness of a gate length for the unevennessΔVth of the voltage of the MOSFET, unevenness of a gate oxide film thickness, and unevenness of a channel dosage.
申请公布号 JPH1187686(A) 申请公布日期 1999.03.30
申请号 JP19970241601 申请日期 1997.09.08
申请人 FUJITSU LTD 发明人 DEURA MANABU
分类号 H01L29/00;H01L21/00;H01L21/336;H01L29/78;(IPC1-7):H01L29/00 主分类号 H01L29/00
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