发明名称 PARALLEL PROCESSOR
摘要 PROBLEM TO BE SOLVED: To continue processing for transmitting/receiving messages before and after the route switching of a network by guaranteeing the order of messages during, before and after the route switching without using time monitoring. SOLUTION: When the transmitting instruction of a message is received from an instruction processor 110, a network interface control part 130 compares a transmission message number showing the number of a message to be next transmitted with a reception confirm message number showing the number of a reception confirmed message through a comparator 135 and inputs the compared result to a transmission control part 133. When the compared result of the comparator 135 does not show transmission stop and there is no other error, either, an ordinary message transmission part 141 performs processing for transmitting an ordinary message. Since the order of messages is guaranteed during, before and after the route switching of the network without using time monitoring, processing for transmitting/receiving the messages can be continued before and after the route switching of the network.
申请公布号 JPH1185716(A) 申请公布日期 1999.03.30
申请号 JP19970235784 申请日期 1997.09.01
申请人 HITACHI LTD 发明人 MAEDA HIROMITSU
分类号 G06F15/16;G06F15/177 主分类号 G06F15/16
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