| 摘要 |
Method and apparatus for selectively controlling interrupt latency in a data processing system (10). In one embodiment, the present invention uses an interrupt control register bit field (50) to determine whether or not execution of an instruction may be interrupted by an interrupt request before execution of the instruction has completed. In some embodiments of the present invention, a first set of instruction may be interrupted mid-execution, while a second set of instructions always complete execution. Which instructions belong to the first set of instructions may be user programmable (e.g. by register bit field 52) or may be fixed. It is advantageous in some data processing systems (10) to define the instructions having the longest execution times as being part of the first set of instructions in order to reduce interrupt latency.
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