发明名称 DISPLAY CONTROL CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To enable high speed receiving of an instruction. SOLUTION: A stack register group 3 storing plural instructions and a buffering controller 2 controlling a busy signal for the outside are provided, the buffering controller 2 generates a busy signal after finish of receiving plural instructions, and the busy signal is released after finish of a whole processing corresponding to plural instructions stored in the stack register group 3.</p>
申请公布号 JPH1185122(A) 申请公布日期 1999.03.30
申请号 JP19970256235 申请日期 1997.09.05
申请人 NEW JAPAN RADIO CO LTD 发明人 KATSU MITSUNORI;FUKUCHI HIROTAKA
分类号 G09G3/36;G09G3/20;G09G5/00;H04N5/66;(IPC1-7):G09G5/00 主分类号 G09G3/36
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