| 摘要 |
PROBLEM TO BE SOLVED: To reduce a circuit scale and also to save power consumption by adding the input signals of the same multiplier by means of a capacitance coupled adding circuit and multiplying the multiplier by means of plural multiplying input capacitors which are selectively connected to the output of the addition result. SOLUTION: The input signals X((N+1)T) are inputted to plural sample-and- hold circuits SHO-SHN which are serially connected in a filter circuit. The respective sample-and-hold circuits hold the input signals sequentially and data of X((N-i)T) is held in the (i+1)-th sample-and-hold circuit SHi . When N is an odd number, X(iT) and X((N-i)T) are multiplied by the same multiplier. When N is an odd number, a multiplying circuit Mi is provided in accordance with SHi and SH( N-i) , data of the same multiplier is inputted to the same multiplying circuit, the total sum of the outputs is calculated by an adding circuitΣand a level is adjusted by a scaler circuit SC.
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