发明名称 REGISTER SET CIRCUIT
摘要 PROBLEM TO BE SOLVED: To make it impossible to set the value lower than the minimumly necessary value. SOLUTION: This circuit is provided with an AND gate 21 for inverting and ANDing out respective data inputted to data input terminals (bit setting terminals) D3-D7 of a register 23 and an OR circuit for ORing this AND gate output and data to an input terminal D2 and outputting the result to the input terminal D2, and when the value higher than 08H is set to a data bus, the set value from the data bus B is inputted to the register 23 with no output from the AND gate 21. When values 07H-04H are set to the data bus, the AND gate 21 outputs '1' but the register 23 is set as the set values are. Further, when a value lower than 03H is set to the data bus, the AND gate 21 outputs '1' to the input terminal D2. Therefore, the minimumly necessary value is set to the register 23 in any case.
申请公布号 JPH1185549(A) 申请公布日期 1999.03.30
申请号 JP19970249261 申请日期 1997.09.16
申请人 MEIDENSHA CORP 发明人 YAMADA KATASHIGE
分类号 G06F11/00 主分类号 G06F11/00
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