| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce wiring resistance and parasitic capacitance and to improve a frequency characteristic by making wiring double layer constitution of a gate electrode material and a source/drain electrode material in a clock line and making another wiring intersecting with the clock lien the same layer as a black matrix. SOLUTION: Clock lines 101-106, a video signal line and a control signal line are made to double layer constitution of a gate electrode material and a source/drain electrode material. Thus, wiring resistance is reduced. Further, by using a wiring material of the same layer as a black matrix on a TFT as the wiring intersecting with these wiring, parasitic capacitance is reduced and a frequency characteristic is improved. Further, by making a wiring interval such as the clock lines, video signal line two times or above of a wiring width, the capacity between the wiring is reduced and the frequency characteristic is improved. Further, by inserting a shield line into between the clock lines and between the video signal lines, mutual interferences between clock lines each other or between video signal lines each other are suppressed.</p> |
