| 摘要 |
<p>According to the present invention, a three-line bus is used for communicati on between a first digital unit (1) and two other digital units (3). The three- line bus includes a system clock line (SCL) as well as a data transmission line (SD) through which data is sent from the two other units (3), i.e. transmitting units, to the first unit (1), i.e. receiving unit. The system uses an authorisation line (WS) for determining which of the two transmittin g units (3) is capable of writing data on the data transmission line (SD) and when it can do so. The communication from the first unit (1), now operating as a transmitter, to the two other units (3), now operating as receivers, is ma de possible by the fact that data signals are also injected in the authorisatio n line (WS) and transmitted through said line together with the authorisation control signals.</p> |
