Modular architecture PET decoder for ATM networks

摘要

A PET decoder for ATM network has a modular architecture composed of a processing unit (PU) having ROM and SRAM memory means and a processing pipeline (build_A, LU_dec, find_Y, find_X) for constructing from a block of m data of a certain number of bits, a square matrix A based on a vector D of relative points over the Galois field (GFÄpÜ), decomposing by triangular factorization the square matrix A and solving the subsystem of equations by simple substitution, and a control unit (CU) interfacing with the ATM network, a programmable parallel processor, a random access memory (RAM) and said processing unit (PU). <IMAGE>