发明名称 |
Phase estimating circuit and demodulating circuit |
摘要 |
<p>The presence or absence of a clock component is detected for an input signal. If the input signal does not comprise a clock component, the operation of a computing circuit is halted, thereby further improving the accuracy of phase estimation. A signal generating circuit(a) produces a twiddle factor for DFT. A DFT circuit(31) performs discrete Fourier transform on an input signal for a predetermined number of symbols based on the twiddle factor for DFT. A pattern detecting circuit(13) examines the input signal for its pattern based on the output from the DFT circuit(31). An averaging filter(32) turns on or off the operation of the subsequent averaging filter(32) according to the detected pattern, and averages the outputs from the DFT circuit(31) to remove a noise component. <IMAGE></p> |
申请公布号 |
EP0903884(A2) |
申请公布日期 |
1999.03.24 |
申请号 |
EP19980111262 |
申请日期 |
1998.06.18 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
SOGABE, YASUSHI;ISHIZU, FUMIO;MURAKAMI, KEISHI |
分类号 |
H04L27/22;H04L7/00;H04L7/027;(IPC1-7):H04L7/027 |
主分类号 |
H04L27/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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