| 摘要 |
PCT No. PCT/JP95/01438 Sec. 371 Date Apr. 25, 1997 Sec. 102(e) Date Apr. 25, 1997 PCT Filed Jul. 20, 1995 PCT Pub. No. WO97/04327 PCT Pub. Date Feb. 6, 1997The present invention aims to take in an external clock signal generated by a device under test into a semiconductor tester and eliminate jitters involved in the clock signal, thereby stabilizes the clock signal, and to use the clock signal as an operation clock of the tester. Hence, a divider A11 which takes the clock signal 21 generated by the device under test as an input, a phase detector circuit 12, a loop filter 13, a VCO 14 and a divider B16 are provided. In addition, the invention includes a test rate generator 15 and an inter-leave circuit 18. The operation clock which is an output of the VCO 14 is input to the test rate generator 15 to output a test rate signal 23, and distributes the test rate signal to the inside circuits as well as feeds back to the phase detector 12 through the divider B16. |
