发明名称 Power-ground plane for a C4 flip-chip substrate
摘要 A package for an integrated circuit that contains a plurality of small circular dielectric spaces which separate vias from a conductive plane of the package. The package has a first internal conductive plane, a second internal conductive plane and a plurality of bond pads located on a top surface of a substrate. The substrate has a plurality of vias that extend through the first conductive plane to couple the second conductive plane to the bond pads. The package has a plurality of concentric dielectric clearance spaces that separate the vias from the first conductive plane. The small concentric spaces optimize the area of the conductive plane to minimize the resistance and maximize the capacitance of the package.
申请公布号 US5886406(A) 申请公布日期 1999.03.23
申请号 US19970946415 申请日期 1997.10.07
申请人 INTEL CORPORATION 发明人 BHANSALI, AMEET
分类号 H01L23/50;H01L23/538;H05K1/02;(IPC1-7):H01L23/04 主分类号 H01L23/50
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