| 摘要 |
Feedback control is performed on the potential of a bit line in accordance with a change in the potential. Meanwhile, the data which has been previously read on the bit line is temporarily latched in a D-type flip-flop. A reference voltage Vref determined by a bias circuit is offset by using an offset circuit while referring to the level of the previously read data latched in the D-type flip-flop. In this manner, a bias voltage is obtained from currently read data, and based on the bias voltage, the potential of the bit line is controlled. Thus, high-speed data determining operation is achieved, which has been previously hampered when the currently read data is reversed with respect to the data read in the previous cycle.
|
