发明名称 Priority switching apparatus of input signal
摘要 An input signal from a Dsub connector and BNC connectors is selected by an analog switch. The frequency of horizontal and vertical synchronizing signals applied from one connector end is measured by a synchronizing frequency detection circuit. The frequencies of horizontal and vertical synchronizing signals applied from the other connector end are converted into voltage values by F/V converters. A microcomputer determines the presence of a synchronizing signal and selects an input signal from the connector end of a high priority level set in a non-volatile memory.
申请公布号 US5886545(A) 申请公布日期 1999.03.23
申请号 US19960711394 申请日期 1996.09.03
申请人 NANAO CORPORATION 发明人 SAKUDA, JUNJI;SAKAI, YOSHIKAZU;HIRAKA, TADAHIKO
分类号 G09G1/16;G09G5/00;G09G5/18;H03K17/00;H04N5/44;(IPC1-7):H03K19/00;H04N5/268 主分类号 G09G1/16
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