发明名称 |
Introducing processing delay as a multiple of the time slot duration |
摘要 |
An apparatus for performance improvement of a burst mode digital wireless receiver has a processing circuit for processing a plurality of received signals and providing a processed signal and a delay circuit for introducing a predetermined delay to the processed signal. The delay circuit is coupled to the processing circuit. The predetermined delay is such that the processed signal is delayed to correspond with a later data burst. The processing circuit weights and combines the received signals, where the processing circuit reduces a mean squared error of an output signal. The processing circuit weights and combines the received signals using a predetermined symbol pattern within a sync sequence within a time slot.
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申请公布号 |
US5887037(A) |
申请公布日期 |
1999.03.23 |
申请号 |
US19960606777 |
申请日期 |
1996.02.27 |
申请人 |
LUCENT TECHNOLOGIES INC. |
发明人 |
GOLDEN, GLENN DAVID;MARTIN, CAROL CATALANO;WINTERS, JACK HARRIMAN |
分类号 |
H04J3/00;H04B7/08;H04B7/26;H04L1/06;(IPC1-7):H04B7/06 |
主分类号 |
H04J3/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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