发明名称 METHOD FOR AVOIDING DEADLOCK OF OBJECT TO BE PROCESSED AND PROCESSOR
摘要 Because wafers are processed kind by kind, some processing chambers are left idle and the entire processing chambers cannot be used efficiently. Since the semiconductor products have been diversified more recently, processing chambers are not used idly if wafers are processed by kinds and the ratio of utilization of the entire processing chambers is lowered, causing a significant decrease of the throughput. A method for avoiding deadlock is characterized in that two transfer paths (a), (b) are set up, the upstream/downstream relationship between the processing chambers (11)-(14) on a path formed by combining the transfer paths (a), (b) is determined an upstream/downstream table representative of the upstream/downstream relationship is prepared, and then it is judged that a wafer will be deadlocked when it is found during the table preparation that the same processing chamber is located on both upstream and downstream sides.
申请公布号 WO9913503(A1) 申请公布日期 1999.03.18
申请号 WO1998JP04083 申请日期 1998.09.10
申请人 TOKYO ELECTRON LIMITED;ISHIZAWA, SHIGERU;SAEKI, HIROAKI 发明人 ISHIZAWA, SHIGERU;SAEKI, HIROAKI
分类号 B65G43/08;G05B19/418;G06Q50/00;G06Q50/04;H01L21/00;H01L21/02;H01L21/677;(IPC1-7):H01L21/68 主分类号 B65G43/08
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