发明名称 |
Memory access control circuit |
摘要 |
The circuit (2) controls nesting whereby an additional access request and data transfer are inserted between an access request and a data transfer for the access request. The control circuit is connected between a memory (8) and a master device (1) and outputs an access request to the memory. There is a device (5) which determines whether nesting can occur.
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申请公布号 |
DE19842677(A1) |
申请公布日期 |
1999.03.18 |
申请号 |
DE19981042677 |
申请日期 |
1998.09.17 |
申请人 |
NEC CORP., TOKIO/TOKYO, JP |
发明人 |
SUZUKI, KAZUMASA, TOKIO/TOKYO, JP |
分类号 |
G06F12/06;G06F13/16;(IPC1-7):G06F13/16;G06F12/02 |
主分类号 |
G06F12/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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