The inventive digital PLL circuit (2) consists of a phase detector (4) which receives an external synchronisation signal (to) and a first feedback signal and produces a phase difference signal. The value of said phase difference signal is a measure of the phase difference between a synchronisation signal (to) and the first feedback signal. The circuit also comprises a DTO (20) which is connected downstream from the phase detector (4), said DTO (20) producing an n-bit wide digital output signal according to the phase difference signal, a feedback device for conveying the output signal of the DTO (20) to the phase detector (4) as a first feedback signal, and a decoding device (14) which is connected to the output of the DTO (20) and which has an output (16) for a correction signal. Said correction signal represents a measure of the phase relation between two scanning values and is derived from at least a subset m of the bits of the second feedback signal. The digital PLL circuit is particularly useful for regenerating horizontal synchronisation in televisions, using the pixel timing.
