| 摘要 |
<p>A system and method is provided having a flash analog-to-digital converter (ADC) that includes an input signal buffer, a plurality of identical voltage comparators, and a reference generator. A clock signal defines the time instances at which the instantaneous input signal voltage is compared against a plurality of reference voltages generated by the reference generator. The individual comparator consists of an integrating amplifier stage followed by an analog latching stage and a digital latch. The integrating amplifier input is allowed to track the input signal continuously. The amplifier output voltage is force to a voltage close to zero before each conversion cycle is initiated by the ADC clock. At the beginning of the conversion cycle, the amplifier output is released and its voltage will follow an excursion related to the integral of the input of the amplifier. At a predefined time moment later, the analog latch is activated. When activated, the analog latch performs a binary decision that exclusively depends on the sign of the amplifier output voltage at the moment of the analog latch activation. The analog latch output may be synchronized with the ADC clock with a digital latch. After a latch period, the amplifier and latch may be reset to zero and the comparator is ready to perform another comparison. In this manner, the analog signal is sampled by use of a sliced integration technique which corresponds to an integral of individual slices of the analog input.</p> |
