发明名称 |
Planarization process for the manufacturing of integrated circuits, particularly for non-volatile semiconductor memory devices |
摘要 |
<p>A planarization process for the manufacturing of integrated circuits, particularly for non-volatile semiconductor memory devices, comprises the steps of: forming a first layer (12) of undoped oxide acting as a barrier layer over a semiconductor substrate (3) wherein integrated devices (M,MC1,MC2) have been previously obtained; forming a second layer (13) of oxide containing phosphor over the first undoped oxide; forming a third layer (14) of oxide containing phosphor and boron over the second oxide layer, the concentration of phosphor being lower than or equal to the concentration of boron; performing a thermal process at a temperature sufficient to melt the third oxide layer (14), to obtain a planar surface. <IMAGE></p> |
申请公布号 |
EP0677869(B1) |
申请公布日期 |
1999.03.17 |
申请号 |
EP19940830167 |
申请日期 |
1994.04.12 |
申请人 |
STMICROELECTRONICS S.R.L. |
发明人 |
LOSAVIO, ALDO;BACCHETTA, MAURIZIO |
分类号 |
H01L21/8247;H01L21/3105;H01L21/316;H01L21/3205;H01L21/768;H01L23/522;H01L29/788;H01L29/792;(IPC1-7):H01L21/310 |
主分类号 |
H01L21/8247 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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