| 摘要 |
<p>PURPOSE:To provide a NOR-type or NAND-type EEPROM. CONSTITUTION:P-channel MOS transistors (T21 and T22) are respectively inserted between level shifters (LS1 and LS2) belonging to a row decoder (an RD) and word lines (W1 and W2) and N-channel MOS transistors (T11 and T12) are respectively connected to the P-channel MOS transistors (T21 and T22). For example, the W1 and the LS1 are turned on and off by the ON-OFF control action of the T21. An erase voltage is applied to either of a source and a drain of the T11 and the other end of the source or the drain is connected to the W1. The ON-OFF control action of the T11 is synchronized with the ON-OFF control action of the T21. The T21 and the like are formed into an N-type well biased to 5 V, for example, and the T11 and the like are formed into a P-type well biased to the erase voltage. This P-type well is formed on the surface of the N-type well. Second level shifters (LS1a and LS2a), which output -16V and 0V to an input of 0V and 5V, are provided and the input and the output of the LS1a are respectively added to a gate of the T21 and a gate of the T11.</p> |
