发明名称
摘要 To provide a new data transmission system between a game device and related peripheral devices, and a device using same. Serial transmission data is divided into an odd-numbered bit sequence and an even-numbered bit sequence. Each bit of the odd-numbered bit sequence data is distributed respectively between pulses of a first pulse sequence signal having a constant interval, thereby forming a first pulse sequence signal (SDCKA). Each bit of the even-numbered bit sequence data is distributed respectively between pulses of a second pulse sequence signal having a constant interval, thereby forming a second pulse sequence signal (SDCKB). The respective time axes are adjusted such that the clock component of the first pulse sequence signal is located in the data section of the second pulse sequence signal, and the clock component of the second pulse sequence signal is located in the data section of the first pulse sequence signal. Data is transmitted using these adjusted first and second pulse sequence signals (SDCKA, SDCKB). <IMAGE>
申请公布号 JP2870538(B2) 申请公布日期 1999.03.17
申请号 JP19980131803 申请日期 1998.05.14
申请人 SEGA ENTAAPURAIZESU KK 发明人 NIITSUMA NAOKI;HIMOTO ATSUNORI
分类号 G06F13/14;A63F13/12;G06F13/38;H01R24/60;H01R24/84;H04L7/00;H04L12/28;H04L25/02;H04L25/14;H04L29/00;H04L29/10;H04Q9/00 主分类号 G06F13/14
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