| 摘要 |
<p>PROBLEM TO BE SOLVED: To shorten the arithmetic processing time of a host processor by sharing a product sum computing element included in a subprocessor also with the host processor. SOLUTION: The arithmetic processing system is provided with a host processor 11, a subprocessor 12 having a product sum computing element 15 and a host bus interface 13 connected between the host processor 11 and the subprocessor 12. The system is provided also with a 1st register 17 for writing a multiplier, a multi-plicand, an operation result, and status, a 2nd register 18 for writing similar data requested from the subprocessor 12 and a switching means or switching the 1st and 2nd registers 17, 18 in accordance with a frequency division signal for dividing the frequency of an inner clock in the system and the product sum computing means 15 in the subprocessor 12 executes product sum operation in accordance with the contents of the switched 1st or 2nd register.</p> |
