Circuit and method for using early reset to prevent CMOS corruption with advanced power supplies

摘要

The reset circuit including a logic gate coupled to an electrical component containing the CMOS memory. The logic gate includes an output and at least a first and second inputs. The first input is configured to receive a first signal indicating that a power-down sequence has been requested. The second input, however, is configured to receive a second signal being a system reset signal. As a result, during a power-down sequence, CMOS memory is precluded from being accessed almost immediately after the first signal has been deactivated while other devices are powered-down in a normal fashion.