Control circuit for a buffer memory to transfer data between systems operating at different speeds

摘要

The present invention relates to a simplified flag control circuitry for use in first in first out (FIFO) memory buffers. The special FIFO memory buffer transfers data between circuits running on different clocks. The present invention delays the initial output of data from the FIFO memory buffer until the memory buffer has received a threshold amount of data. After the threshold quantity of data has been received, the present invention allows output of data from the FIFO.