发明名称 |
Behavioral language models for testing and verification of digital electronic circuits |
摘要 |
A behavioral language-based methodology for the verification and testing of digital circuit designs. An automated or interactive simulation verification system can be used in accordance with the methodology to verify a digital circuit on inexpensive, simple digital circuit simulators, using behavioral languages, and achieve certain performance features found only on more costly, complex simulators.
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申请公布号 |
US5883809(A) |
申请公布日期 |
1999.03.16 |
申请号 |
US19960688818 |
申请日期 |
1996.07.26 |
申请人 |
3 COM CORPORATION |
发明人 |
SULLIVAN, RONALD JOSEPH;ZROKA, MICHAEL JOHN |
分类号 |
G01R31/3183;G06F17/50;(IPC1-7):G06F17/00 |
主分类号 |
G01R31/3183 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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