SEMICONDUCTOR MEMORY DEVICE

摘要

PROBLEM TO BE SOLVED: To detect the short conditions between neighboring word lines or bit lines by providing testing memory cell arrays composed of plural testing memory cells installed for each main bit line and testing word lines that simultaneously select this memory cell. SOLUTION: The bit line testing memory cell array 120 is provided with bit line testing memory cells BM(0)-BM(n) composed from n+1 MOS transistors and the gate of each transistor is connected to respective bit line testing word lines WLET. The drains corresponding to odd number memory cells are connected to the main bit lines and the drains for even number memory cells are floating. By the input of a testing signal WSBT, the odd number bit lines become conducting to be brought to a low level and even number bit lines reach a high level. When short exists between neighboring bit lines, these bit lines are brought to a low level.