发明名称 CLOCK SELECTION SYSTEM IN DATA TRANSMITTER
摘要 PROBLEM TO BE SOLVED: To provide a clock selection system in the data transmitter where self-running of a clock signal is prevented for the data transmitter, the affinity with a host device is ensured and the reliability of the clock signal is enhanced. SOLUTION: Usually a clock signal of a clock supply device 19 is received by an in-station clock reception section 14b of the data transmitter 14 to provide an output of the generated clock to activate an in-station interface section 20 via a clock changeover section 14c, and when a clock signal of the in-station clock supply device 19 is missing, reception signal from a host device 13 received by an interface section 16 of a subscriber terminal are given to the data transmitter 14 and a clock extract section 14a of the data transmitter 14 extracts the clock signal and a clock changeover section 14c selects the clock and a clock signal belonging to a host device 13 activates the in-station interface section 20 to activate a subscriber 17 and other device 18 or the like.
申请公布号 JPH1175275(A) 申请公布日期 1999.03.16
申请号 JP19970249725 申请日期 1997.08.29
申请人 ANDO ELECTRIC CO LTD 发明人 KATO JUNICHI;YAGI YUTAKA
分类号 H04L7/00;H04L12/28;H04L12/70;H04Q3/00;H04Q11/04 主分类号 H04L7/00
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