| 摘要 |
PROBLEM TO BE SOLVED: To attain efficient and economical design by making it unnecessary to provide the dummy delay circuit of a clock driver, making it unnecessary to operate the design of a clock driver dummy for each wiring design change even at the time of applying this circuit to a device in which the clock delay amounts of an ASIC or the like are different for each chip, or making it unnecessary to consider the layout of an area for clock driver dummy. SOLUTION: This circuit is provided with a first delay circuit column 1 for allowing a pulse or a pulse edge to progress in a constant period, a second delay circuit column 2 for allowing a pulse or a pulse edge to pass in length proportional to the length in which the pulse or the pulse edge progresses in the first delay circuit, and a circuit 9 for outputting the monitor signal of a period when a clock pulse progresses in a clock driver. The first delay circuit 1 is formed of a clocked invertor or the like, and the progress of the pulse or the edge in the first delay circuit is stopped in an arbitrary timing during the output of the monitor signal. |
