Process for manufacturing an integrated CMOS circuit

摘要

PCT No. PCT/DE96/01202 Sec. 371 Date Jan. 9, 1998 Sec. 102(e) Date Jan. 9, 1998 PCT Filed Jul. 4, 1996 PCT Pub. No. WO97/03462 PCT Pub. Date Jan. 30, 1997In the production of a dual work function CMOS circuit, a polysilicon layer is produced for the purpose of forming a gate structure, the average grain diameter of which polysilicon layer is greater than the minimum extent in the gate structure, in order to suppress lateral dopant diffusion. In particular, a constriction having a width less than the average grain diameter is produced in the gate structure.