Temporal re-alignment of a floating point pipeline to an integer pipeline for emulation of a load-operate architecture on a load/store processor

摘要

A processor that can execute both CISC and RISC instructions has an integer pipeline and a floating point pipeline. RISC instructions are sent to the floating point pipeline at the beginning of the integer pipeline, but CISC instructions re-align the floating point pipeline. CISC instructions are sent to the floating point pipeline near the end of the integer pipeline to allow the integer pipeline to fetch memory operands for the floating point pipeline. Thus the floating point pipeline relies on the memory operand fetch facilities of the integer pipeline. Complex CISC fetch-operate instructions pass through the integer pipeline first to fetch a floating point operand, and then begin the floating point pipeline for execution of a floating point operation. However, RISC instructions only use register operands and can begin the floating point pipeline earlier, reducing latency until the floating point result is produced. Rapid re-configuration of the pipeline alignment between a pipeline optimized for RISC instructions and one optimized for CISC instructions is possible with muxes and a mode register. Exception handling and pipeline coordination are also described.