发明名称 COMPRESSED INPUT BIT STREAM PROCESSOR
摘要 PROBLEM TO BE SOLVED: To provide a video processing system capable of performing a decoding processing to a bit stream at any compressed state and generating an output bit stream with the same or different compressed state as an input bit stream. SOLUTION: The system is provided with a multilayer decoder 114 including plural decoding modules to decode the input bit stream, a processor to generate a corrected bit stream by executing a desired processing to the decoded bit stream and a multilayer encoder 124 including plural encoding modules to generate a compressed output bit stream by re-encoding the corrected bit stream. Calculation processing resources to become necessary for the case that all bit streams are decoded and encoded are saved and the bit stream at any compressed state is simultaneously inputted and outputted by stopping a decoding operation at a rear stage as completion of decoding of a desired decoding level by the multilayer decoder 114 and encoding the bit stream from the level corresponding to a decoding stage by the mulilayer encoder 124.
申请公布号 JPH1174798(A) 申请公布日期 1999.03.16
申请号 JP19980174399 申请日期 1998.06.22
申请人 HEWLETT PACKARD CO <HP> 发明人 LIU SAM J
分类号 H03M7/30;H04N7/26;(IPC1-7):H03M7/30;H04N7/24 主分类号 H03M7/30
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