| 摘要 |
PROBLEM TO BE SOLVED: To attain high speed bit correlation processing, miniaturization and low power consumption. SOLUTION: A shift register 1 receives frame data 5 synchronously with a clock 6 in the unit of 48 bits and provides an output of parallel data 7, 7a, 7b in the unit of 16 bits. Different bit number calculation ROMs 2, 2a, 2b calculate a difference bit number from the parallel data 7, 7a, 7b. An adder ROM 3 adds 16-bit difference bit number data 8, 8a, 8b outputted from the different bit number calculation ROMs 2, 2a, 2b to provide different bit number data 9 being a result of sum. |
