发明名称 Method and apparatus for simultaneous memory subarray testing
摘要 One row of memory cells per sense amplifier bank on a multiple subarray dynamic random access memory (DRAM) are fired while in a test mode. Multiplexors are provided on local I/O lines to ensure that the local I/O lines are not connected to global I/O lines when multiple rows are fired. This provides protection for I/O circuitry not designed to handle the load of multiple local I/O lines coupled in parallel. The multiplexors are controlled by a multiplexor control signal which is separate from row and column decode signals. During a refresh/hammer test, such rows are fired as many times as possible during a refresh period. Then adjacent rows are tested to determine if they were affected by the firing. During the firing, the multiplexors effectively isolate global I/O lines from local I/O lines.
申请公布号 US5883849(A) 申请公布日期 1999.03.16
申请号 US19970885535 申请日期 1997.06.30
申请人 MICRON TECHNOLOGY, INC. 发明人 SHIRLEY, BRIAN M.
分类号 G11C11/4096;G11C29/02;G11C29/10;G11C29/34;(IPC1-7):G11C8/00 主分类号 G11C11/4096
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