The device (1000) has a memory cell field including a bipolar transistor (BT1) whose base is connected to a node between the source of two memory cell transistors (MT1a,b). A memory cell SL decoder (132) controls the potential of an emitter of the bipolar transistor. The collector of the bipolar transistor is held at ground potential. E- In a read operation, the emitter potential is controlled so that the bipolar transistor enters an on state and a current flowing through a channel of one of the memory cell transistors is amplified by the bipolar transistor to enable it to be read.
