发明名称 CIRCUIT AND METHOD FOR MINIMISING BIT ERRORS
摘要 The invention relates to a circuit and a method for minimising bit errors. Corresponding bits of a bit sequence are compared with the corrected bit sequence or an error signal. If they do not correspond, the adjacent bits of the corrected bit sequence are used to correct a decision criterion made up of a scanning time and a threshold value.
申请公布号 CA2302274(A1) 申请公布日期 1999.03.11
申请号 CA19982302274 申请日期 1998.08.18
申请人 SIEMENS AKTIENGESELLSCHAFT 发明人 STOLL, DETLEF
分类号 H04L25/08;H04L7/033;H04L7/04;H04L25/06;(IPC1-7):H04L25/06 主分类号 H04L25/08
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